An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding.
Yeong-Luh UengBo-Jhang YangChung-Jay YangHuang-Chang LeeJeng-Da YangPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2013)
Keyphrases
- low density parity check
- ldpc codes
- decoding algorithm
- embedded systems
- single chip
- video decoder
- hardware architecture
- real time
- design process
- low cost
- hardware and software
- turbo codes
- vlsi architecture
- error correction
- hardware design
- hardware implementation
- low power
- vlsi implementation
- fpga implementation
- low complexity