A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes.
Yeong-Luh UengChung-Jay YangKuan-Chieh WangChun-Jung ChenPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2010)
Keyphrases
- ldpc codes
- high rate
- decoding algorithm
- joint source channel decoding
- error correction
- low density parity check
- message passing
- false alarms
- image transmission
- belief propagation
- channel coding
- source coding
- rate allocation
- false negative
- information theoretic
- end to end
- vlsi architecture
- non binary
- false positives
- motion estimation
- coding scheme
- computer simulation
- image compression