Chong S. Rim

Publication Activity (10 Years)

Years Active: 1989-2010
Publications (10 Years): 0

Publications

Saejoon Kim, Seunghyuk Lee, Jun Heo, Chong S. Rim
Adaptive Mixed Scheduling for Correcting Errors in Trapping Sets of LDPC Codes. IEEE Commun. Lett. 14 (7) (2010)
Young-Jun Cha, Chong S. Rim, Kazuo Nakajima
SEGRA: a very fast general area router for multichip modules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (5) (1999)
Yhonkyong Choi, Chong S. Rim
Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards. CICC (1999)
Jagannathan Narasimhan, Kazuo Nakajima, Chong S. Rim
A Graph Theoretical Approach for the Yield Enhancement of Reconfigurable VLSI/WSI Arrays. Discret. Appl. Math. 90 (1-3) (1999)
Young-Jun Cha, Chong S. Rim, Kazuo Nakajima
A simple and effective greedy multilayer router for MCMs. ISPD (1997)
Yanghoon Kim, Chong S. Rim, Byoungki Min
A Block Matching Algorithm with 16: 1 Subsampling and Its Hardware Design. ISCAS (1995)
Jagannathan Narasimham, Kazuo Nakajima, Chong S. Rim, Anton T. Dahbura
Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (8) (1994)
Yhonkyong Choi, Juhyun Lee, Chong S. Rim
Automatic Functional Cell Generation in the Sea-of-Gates Layout Style. ISCAS (1994)
Ruey-Der Lou, Majid Sarrafzadeh, Chong S. Rim, Kazuo Nakajima, Sumio Masuda
General Circular Permutation Layout. Math. Syst. Theory 25 (4) (1992)
Hyeong-Ah Choi, Kazuo Nakajima, Chong S. Rim
Graph Bipartization and via Minimization. SIAM J. Discret. Math. 2 (1) (1989)
Chong S. Rim, Toshinobu Kashiwabara, Kazuo Nakajima
Exact algorithms for multilayer topological via minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (11) (1989)