Chiu-Sing Choy

Publication Activity (10 Years)

Years Active: 1997-2020
Publications (10 Years): 5

Top Topics

Hardware Implementation

Data Compression

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Instrum. Meas.

Publications

Huan Wu, Hongda Wang, Chester Shu, Chiu-Sing Choy, Chao Lu
BOTDA Fiber Sensor System Based on FPGA Accelerated Support Vector Regression. IEEE Trans. Instrum. Meas. 69 (6) (2020)
Huan Wu, Hongda Wang, Chester Shu, Chiu-Sing Choy, Chao Lu
Brillouin Optical Time Domain Analyzer Fiber Sensor Based on FPGA Accelerated Support Vector Regression. OFC (2019)
Weiwei Shi, Yuan Xu, Chiu-Sing Choy, Zhiyong Chen, Junwei Yang, Robert K. F. Teng, Mei Jiang, X. Deng
A 0.4 V 298 nJ/op Neural Signal Spectral Feature Extraction Module With Novel Approximate MACs and Custom Compressors. IEEE Trans. Circuits Syst. II Express Briefs (10) (2019)
Hongda Wang, Weiwei Shi, Chiu-Sing Choy
Hardware Design of Real Time Epileptic Seizure Detection Based on STFT and SVM. IEEE Access 6 (2018)
Weiwei Shi, Hai-Peng Wang, Chiu-Sing Choy, Junwei Yang, Mei Jiang, Robert K. F. Teng, Mingcheng Zhu
A 0.35 V 376 Mb/s Configurable Long Integer Multiplier for Subthreshold Encryption. IEEE Trans. Circuits Syst. II Express Briefs (10) (2018)
Hao Wang, Jianfeng Wang, Chiu-Sing Choy
A 2.5-Mbps, 170-cm transmission distance IntraBody communication receiver front end design and its synchronization technique research. MWSCAS (2014)
Hao Wang, Chiu-Sing Choy
A novel high speed, low power IntraBody Communication Receiver Front End based on sampling rate boosting switched-capacitor filter. MWSCAS (2014)
Yanqing Ai, Chiu-Sing Choy
A data compression based power aware BAN system exploration of IEEE 802.15.6. ISCE (2013)
Kong-Pang Pun, Wang Tung Cheng, Chiu-Sing Choy, Cheong-fat Chan
A 75-dB image rejection IF-input quadrature-sampling SC ΣΔ Modulator. IEEE J. Solid State Circuits 41 (6) (2006)
Wang Tung Cheng, Kong-Pang Pun, Chiu-Sing Choy, Cheong-Fat Chan
A 75dB image rejection IF-input quadrature sampling SC ΣΔ modulator. ESSCIRC (2005)
Kin-Pui Ho, Cheong-Fat Chan, Chiu-Sing Choy, Kong-Pang Pun
Reversed nested Miller compensation with voltage buffer and nulling resistor. IEEE J. Solid State Circuits 38 (10) (2003)
Pui-Lam Siu, Chiu-Sing Choy, Chi Fat Chan, Kong-Pang Pun
A contactless smartcard designed with asynchronous circuit technique. ESSCIRC (2003)
Jan Butas, Chiu-Sing Choy, Juraj Povazanec, Cheong-Fat Chan
Asynchronous cross-pipelined multiplier. IEEE J. Solid State Circuits 36 (8) (2001)
Jing-Ling Yang, Chiu-Sing Choy, Cheong-Fat Chan
A self-timed divider using a new fast and robust pipeline scheme. IEEE J. Solid State Circuits 36 (6) (2001)
Wing-Sum Mak, Cheong-Fa Chan, Ka-Wai Cheung, Chiu-Sing Choy
An 8×8 adiabatic quasi-static CMOS multiplier. ISCAS (2000)
Vincent Wing-Yun Sit, Chiu-Sing Choy, Cheong-Fat Chan
A four-phase handshaking asynchronous static RAM design for self-timed systems. IEEE J. Solid State Circuits 34 (1) (1999)
Juraj Povazanec, Chiu-Sing Choy, Cheong-fat Chan
Asynchronous logic in bit-serial arithmetic. ICECS (1998)
Chiu-Sing Choy, M. H. Ku, Chi Fat Chan
A low power-noise output driver with an adaptive characteristic applicable to a wide range of loading conditions. IEEE J. Solid State Circuits 32 (6) (1997)