Juraj Povazanec

Publication Activity (10 Years)

Years Active: 1996-2002
Publications (10 Years): 0

Publications

Jayasanker Jayabalan, Juraj Povazanec
Integration of SRAM Redundancy into Production Test. ITC (2002)
Jan Butas, Chiu-Sing Choy, Juraj Povazanec, Cheong-Fat Chan
Asynchronous cross-pipelined multiplier. IEEE J. Solid State Circuits 36 (8) (2001)
Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-fat Chan
A New Control Circuit for Asynchronous Micropipelines. IEEE Trans. Computers 50 (9) (2001)
Vinod Nair, Martin Erdmann, Shridhar Mubaraq Mishra, Juraj Povazanec, Amit Shaligram, Chun Feng Hu
A single chip terminal solution for high-end telephone applications. CICC (2001)
Juraj Povazanec, Oliver Chiu-sing Choy, Cheong-fat Chan, Jan Butas, Yeu-qiu Zhang, Jing-ling Yang, Tin-yan Tang
Pipelined Dataflow Architecture of a Small Processor. PDPTA (1999)
Juraj Povazanec, Chiu-Sing Choy, Cheong-fat Chan
Asynchronous logic in bit-serial arithmetic. ICECS (1998)
Oliver Chiu-sing Choy, Tin-Chak Johnson Pang, Juraj Povazanec, Cheong-fat Chan
A Useful Micropipeline Architecture to Implement DSP Algorithms. EUROMICRO (1998)
Juraj Povazanec, Vladislav Musil
Fault and test-process modelling for integrated circuits. J. Syst. Archit. 43 (1-5) (1997)
Jiri Kaderka, Vladislav Musil, Juraj Povazanec, Petr Simek
Neural network based system for testing and diagnostics of analogue integrated circuits. ICECS (1996)
Juraj Povazanec, Jirí Kaderka, Vladislav Musil, Petr Simek
Test-Process Simulation with Neural Network Evaluation. ESM (1996)