Chien-Hsing Wu

Publication Activity (10 Years)

Years Active: 1995-2017
Publications (10 Years): 1

Top Topics

Parameter Tuning

Computationally Efficient

Top Venues

Wirel. Pers. Commun.

Publications

Chia-Peng Chou, Tsung-Hsien Liu, Chien-Hsing Wu
Robust Training Symbol Assisted Least Squares Estimation for Direct Conversion Receivers with Oscillator IQ-Imbalance. Wirel. Pers. Commun. 95 (2) (2017)
Chia-Peng Chou, Chien-Hsing Wu, Tsung-Hsien Liu, Yin-Tsung Hwang
Space-Frequency-Coded MIMO OFDM Receivers Based on Gaussian Message Passing. ICC (2009)
Chien-Hsing Wu, Yan-Chr Tsai, Hwa-Long Tsai
Quantum circuits for stabilizer codes. ISCAS (3) (2005)
Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen
VLSI architectural design tradeoffs for sliding-window log-MAP decoders. IEEE Trans. Very Large Scale Integr. Syst. 13 (4) (2005)
Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). IEEE Trans. Computers 53 (3) (2004)
Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo
VLSI architecture exploration for sliding-window Log-MAP decoders. ISCAS (2) (2004)
Yin-Tsung Hwang, Kuo-Wei Liao, Chien-Hsing Wu
FPGA realization of an OFDM frame synchronization design for dispersive channels. ISCAS (2) (2003)
Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
) for secure communication. ISCAS (5) (2002)
Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu
Memory arrangements in turbo decoders using sliding-window BCJR algorithm. ISCAS (5) (2002)
Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2002)
Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. ISCAS (4) (2001)
Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu
VLSI architecture of extended in-place path metric update for Viterbi decoders. ISCAS (4) (2001)
Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu
An efficient approach for in-place scheduling of path metric update in Viterbi decoders. ISCAS (2000)
Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu
A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. ISCAS (1) (1999)
Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu
An area-efficient versatile Reed-Solomon decoder for ADSL. ISCAS (1) (1999)
Yin-Hwa Huang, Yuo-Chuan Chang, Chi-Shyan Wu, Chien-Hsing Wu
Design of an MPEG-based set-top box for video on demand services. ICASSP (1995)