VLSI architecture of extended in-place path metric update for Viterbi decoders.

Chien-Ming Wu Ming-Der Shieh Chien-Hsing Wu Ming-Hwa Sheu

Published in: ISCAS (4) (2001)

Keyphrases

vlsi architecture
vlsi implementation
low complexity
low power
real time
shortest path
neural network
high speed
decoding algorithm