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Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design.

Chien-Hsing WuChien-Ming WuMing-Der ShiehYin-Tsung Hwang
Published in: ISCAS (4) (2001)
Keyphrases
  • low complexity
  • vlsi architecture
  • computational complexity
  • high speed
  • np hard
  • vlsi implementation
  • computational load
  • single pass
  • mode decision
  • machine learning
  • three dimensional
  • optimal solution