Chia-Pin R. Liu

Publication Activity (10 Years)

Years Active: 1999-2009
Publications (10 Years): 0

Publications

Chia-Pin R. Liu
Floorplan Optimization for Hierarchical VLSI Design. CAINE (2009)
Chia-Pin R. Liu
A Novel Floorplanning for Hierarchical VLSI Design. CATA (2009)
Chia-Pin R. Liu
A Novel Synthesis for Dynamic CMOS Circuits. CAINE (2008)
Chia-Pin R. Liu
Gate Model Extraction from CMOS Transistor Circuits. CAINE (2007)
Chia-Pin R. Liu, Shaofeng Yang, Mahmound A. Manzoul
Traffic Monitoring for a Network Visualization Environment. CATA (2006)
Chia-Pin R. Liu
Transistor-mapped binary decision diagram for CMOS circuits. CAINE (2006)
Chia-Pin R. Liu, Jacob A. Abraham
Transistor Level Synthesis for Static CMOS Combinational Circuits. Great Lakes Symposium on VLSI (1999)