Chi-Chou Kao

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 7

Top Topics

Convolutional Neural Network

Reconfigurable Architecture

Processing Elements

Top Venues

Multim. Tools Appl.

J. Circuits Syst. Comput.

J. Signal Process. Syst.

IEEE Trans. Parallel Distributed Syst.

Publications

Chi-Chou Kao
Performance-oriented FPGA-based convolution neural network designs. Multim. Tools Appl. 82 (14) (2023)
Chi-Chou Kao
Optimizing FPGA-Based Convolutional Neural Network Performance. J. Circuits Syst. Comput. 32 (15) (2023)
Chi-Chou Kao
Performance-driven parallel reconfigurable computing architecture for multi-standard video decoding. Multim. Tools Appl. 79 (41-42) (2020)
Chi-Chou Kao
Resource and Performance Tradeoff for Task Scheduling of Parallel Reconfigurable Architectures. J. Circuits Syst. Comput. 29 (2) (2020)
Chi-Chou Kao
Design and Implementation of Stereoscopic Image Generation. J. Circuits Syst. Comput. 28 (8) (2019)
Chi-Chou Kao
Stereoscopic image generation with depth image based rendering. Multim. Tools Appl. 76 (11) (2017)
Chi-Chou Kao, Yi-Ciang Lin
Designs of Low Power Snoop for Multiprocessor System on Chip. J. Signal Process. Syst. 88 (1) (2017)
Chi-Chou Kao
Clock Skew Minimization in Multiple Dynamic Supply Voltage with Adjustable Delay Buffers Restriction. J. Signal Process. Syst. 79 (1) (2015)
Chi-Chou Kao
Performance-Oriented Partitioning for Task Scheduling of Parallel Reconfigurable Architectures. IEEE Trans. Parallel Distributed Syst. 26 (3) (2015)
Chi-Chou Kao, Yen-Tai Lai
Improved Time-Multiplexed FPGA Architecture and Algorithm for Minimizing Communication Cost Designs. J. Circuits Syst. Comput. 22 (5) (2013)
Chi-Chou Kao
E-Health Design of EEG Signal Classification for Epilepsy Diagnosis. ISBAST (2013)
Chi-Chou Kao, Yen-Tai Lai, Chao-Feng Tseng
Laplacian-based H.264 intra-prediction mode decision. CHINACOM (2012)
Wen-Lin Yang, Chi-Chou Kao, Cheng-Huang Tung
Heuristic Algorithms for Constructing Interference-Free and Delay-Constrained Multicast Trees for Wireless Mesh Networks. KSII Trans. Internet Inf. Syst. 5 (2) (2011)
Chi-Chou Kao
BDD-based synthesis for mixed CMOS/PTL logic. Int. J. Circuit Theory Appl. 39 (9) (2011)
Chi-Chou Kao, Yen-Tai Lai, Chia-Hui Lin
An efficient reflection invariance region-based image retrieval framework. Int. J. Imaging Syst. Technol. 20 (2) (2010)
Yen-Tai Lai, Chi-Chou Kao, Tzu-Chiang Tai, Wen-Chun Yeh
A Performance-Driven Rotational Invariant Image Retrieval System. J. Inf. Sci. Eng. 26 (6) (2010)
Yen-Tai Lai, Chia-Nan Yeh, Chi-Chou Kao
A Novel Digital Pixel Sensor System. ISCAS (2009)
Chi-Chou Kao
Computer-aided crosstalk minimisation design for system-on-chip. IET Comput. Digit. Tech. 2 (1) (2008)
Chi-Chou Kao
A High Flexibility Design for Clock Distribution Network in System on Chip. J. Circuits Syst. Comput. 16 (1) (2007)
Chi-Chou Kao, Yen-Tai Lai
An efficient algorithm for finding the minimal-area FPGA technology mapping. ACM Trans. Design Autom. Electr. Syst. 10 (1) (2005)
Chi-Chou Kao, Yen-Tai Lai
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction. ASP-DAC (2004)
Chi-Chou Kao
Design of echo cancellation and noise elimination for speech enhancement. IEEE Trans. Consumer Electron. 49 (4) (2003)
Chi-Chou Kao, Yen-Tai Lai
A technology mapping algorithm for heterogeneous FPGAs. ASP-DAC (2003)
Chi-Chou Kao, Yen-Tai Lai
A routability and performance driven technology mapping algorithm for LUT based FPGA designs. ISCAS (1) (1999)
Yen-Tai Lai, Chi-Chou Kao, Wu-Chien Shieh
A quadratic programming method for interconnection crosstalk minimization. ISCAS (6) (1999)