A routability and performance driven technology mapping algorithm for LUT based FPGA designs.
Chi-Chou KaoYen-Tai LaiPublished in: ISCAS (1) (1999)
Keyphrases
- experimental evaluation
- learning algorithm
- dynamic programming
- detection algorithm
- preprocessing
- search space
- theoretical analysis
- times faster
- computational complexity
- np hard
- k means
- cost function
- high accuracy
- hardware implementation
- significant improvement
- low cost
- tree structure
- expectation maximization
- optimization algorithm
- mapping function
- matching algorithm
- real time
- particle swarm optimization
- input data
- worst case
- probabilistic model
- evolutionary algorithm
- objective function