Chen Yang

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 30

Top Topics

Convolutional Neural Network

Automatically Generate

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

J. Circuits Syst. Comput.

Publications

Chen Yang, Yishuo Meng, Jiawei Xi, Siwei Xiang, Jianfei Wang, Kuizhi Mei
WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 32 (1) (2024)
Chen Yang, Yaoyao Yang, Yishuo Meng, Kaibo Huo, Siwei Xiang, Jianfei Wang, Li Geng
Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (3) (2024)
Fahong Zhang, Chen Yang, Rui Zong, Xinran Zheng, Jianfei Wang, Yishuo Meng
An Efficient and Scalable FHE-Based PDQ Scheme: Utilizing FFT to Design a Low Multiplication Depth Large-Integer Comparison Algorithm. IEEE Trans. Inf. Forensics Secur. 19 (2024)
Yishuo Meng, Siwei Xiang, Jianfei Wang, Jia Hou, Chen Yang
ALSCA: A Large-Scale Sparse CNN Accelerator Using Position-First Dataflow and Input Channel Merging Approach. IEEE Trans. Circuits Syst. II Express Briefs 71 (7) (2024)
Jianfei Wang, Chen Yang, Fahong Zhang, Jia Hou, Yishuo Meng, Siwei Xiang, Yang Su
A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture. IEEE Trans. Circuits Syst. II Express Briefs 71 (4) (2024)
Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Siwei Xiang, Yang Su
A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (1) (2024)
Chen Yang, Kaibo Huo, Long-Fei Geng, Kuizhi Mei
DRGN: a dynamically reconfigurable accelerator for graph neural networks. J. Ambient Intell. Humaniz. Comput. 14 (7) (2023)
Chen Yang, Junfeng Wu, Siwei Xiang, Liyan Liang, Li Geng
A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access. IEEE Trans. Very Large Scale Integr. Syst. 31 (10) (2023)
Jia Hou, Jingyu Zhang, Qi Chen, Siwei Xiang, Yishuo Meng, Jianfei Wang, Cimang Lu, Chen Yang
POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection. Inf. 14 (11) (2023)
Yifan Gong, Jinshuo Zhang, Xin Liu, Jialin Li, Ying Lei, Zhe Zhang, Chen Yang, Li Geng
A Real-Time and Efficient Optical Flow Tracking Accelerator on FPGA Platform. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Yuheng Xia, Yishuo Meng, Siwei Xiang, Jianfei Wang, Chen Yang
An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method. ICTA (2023)
Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Yang Su
TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 31 (8) (2023)
Yishuo Meng, Chen Yang, Siwei Xiang, Jianfei Wang, Kuizhi Mei, Li Geng
An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow. IEEE Trans. Very Large Scale Integr. Syst. 31 (10) (2023)
Yang Su, Bai-Long Yang, Chen Yang, Zepeng Yang, Yi-Wei Liu
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication. IEEE Trans. Very Large Scale Integr. Syst. 30 (8) (2022)
Chen Yang, Qi Chen, Yaoyao Yang, Jingyu Zhang, Minshun Wu, Kuizhi Mei
SDF-SLAM: A Deep Learning Based Highly Accurate SLAM Using Monocular Camera Aiming at Indoor Map Reconstruction With Semantic and Depth Fusion. IEEE Access 10 (2022)
Chen Yang, Yishuo Meng, Kaibo Huo, Jiawei Xi, Kuizhi Mei
A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers. IEEE Trans. Very Large Scale Integr. Syst. 30 (12) (2022)
Yang Su, Bai-Long Yang, Chen Yang, Songyin Zhao
ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (7) (2022)
Chen Yang, Jia Hou, Yizhou Wang, Haibo Zhang, Xiaoli Wang, Li Geng
RNA: A Flexible and Efficient Accelerator Based on Dynamically Reconfigurable Computing for Multiple Convolutional Neural Networks. J. Circuits Syst. Comput. 31 (16) (2022)
Chen Yang, Jingyu Zhang, Qi Chen, Yi Xu, Cimang Lu
UL-CNN: An Ultra-Lightweight Convolutional Neural Network Aiming at Flash-Based Computing-In-Memory Architecture for Pedestrian Recognition. J. Circuits Syst. Comput. 30 (2) (2021)
Chen Yang, Zepeng Yang, Jia Hou, Yang Su
A Lightweight Full Homomorphic Encryption Scheme on Fully-connected Layer for CNN Hardware Accelerator achieving Security Inference. ICECS (2021)
Chen Yang, Jia Hou, Yizhou Wang, Li Geng
CRP: Context-directed Replacement Policy to Improve Cache Performance for Coarse-Grained Reconfigurable Arrays. ICECS (2020)
Chen Yang, Yizhou Wang, Xiaoli Wang, Li Geng
A Stride-Based Convolution Decomposition Method to Stretch CNN Acceleration Algorithms for Efficient and Flexible Hardware Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2020)
Yang Su, Bailong Yang, Chen Yang, Luogeng Tian
FPGA-Based Hardware Accelerator for Leveled Ring-LWE Fully Homomorphic Encryption. IEEE Access 8 (2020)
Chen Yang, Jia Hou, Yizhou Wang, Qi Zhou, Li Geng
CCP: Configuration Context based Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. ICECS (2019)
Chen Yang, Bowen Li, Yizhou Wang
A Fully Quantitative Scheme With Fine-grained Tuning Method For Lightweight CNN Acceleration. ICECS (2019)
Chen Yang, Yizhou Wang, Xiaoli Wang, Li Geng
WRA: A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
Leibo Liu, Chen Yang, Shouyi Yin, Shaojun Wei
CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (6) (2018)
Leibo Liu, Zhaoshi Li, Chen Yang, Chenchen Deng, Shouyi Yin, Shaojun Wei
HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing. IEEE Trans. Circuits Syst. II Express Briefs (3) (2018)
Chen Yang, Leibo Liu, Kai Luo, Shouyi Yin, Shaojun Wei
CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays. IEEE Trans. Parallel Distributed Syst. 28 (1) (2017)
Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei
Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays. DAC (2016)
Chen Yang, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, Shaojun Wei
Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array. J. Circuits Syst. Comput. 24 (3) (2015)
Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei
Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only). FPGA (2015)
Chen Yang, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, Shaojun Wei
Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor. FPL (2014)