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A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication.
Yang Su
Bai-Long Yang
Chen Yang
Zepeng Yang
Yi-Wei Liu
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2022)
Keyphrases
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hardware implementation
real time
dynamic reconfiguration
network architecture
neural network
computation intensive
functional units
architectural design
low order
general purpose
unified model
data exchange
cloud computing
low cost
reconfigurable hardware
learning algorithm
reconfigurable architecture