Camille Diou

Publication Activity (10 Years)

Years Active: 1999-2021
Publications (10 Years): 5

Top Topics

Metaheuristic Algorithms

Communication Delays

Feature Extraction

Top Venues

Ann. des Télécommunications

Publications

Christophe Hüseyin Kizil, Camille Diou, Camel Tanougast
Time-shift immunity for wireless sensor network based on discrete wavelet packets. Ann. des Télécommunications 76 (1-2) (2021)
Fadel Abdallah, Camel Tanougast, Imed Kacem, Camille Diou, Daniel Singer
Genetic algorithms for scheduling in a CPU/FPGA architecture with heterogeneous communication delays. Comput. Ind. Eng. 137 (2019)
Fadel Abdallah, Camel Tanougast, Imed Kacem, Camille Diou, Daniel Singer
A comparison of two metaheuristic algorithms for scheduling problem on a heterogeneous CPU/FPGA architecture with communication delays. CoDIT (2017)
Hayat Daoud, Camel Tanougast, Mostefa Belarbi, Mikael Heil, Camille Diou
Formal Proof of the Dependable Bypassing Routing Algorithm Suitable for Adaptive Networks on Chip QnoC Architecture. Syst. 5 (1) (2017)
Mohamed Tabaa, Camille Diou, Rachid Saadane, Abbas Dandache
LOS/NLOS Identification Based on Stable Distribution Feature Extraction and SVM Classifier for UWB On-Body Communications. J. Ubiquitous Syst. Pervasive Networks 6 (1) (2015)
Mohamed Tabaa, Camille Diou, Rachid Saadane, Abbas Dandache
LOS/NLOS Identification based on Stable Distribution Feature Extraction and SVM Classifier for UWB On-body Communications. ANT/SEIT (2014)
Mohamed Tabaa, Camille Diou
A low-cost many-to-one WSN architecture based on UWB-IR and DWPT. CoDIT (2014)
Mohsin Amin, Abbas Ramazani, Fabrice Monteiro, Camille Diou, Abbas Dandache
A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture. Int. J. Reconfigurable Comput. 2011 (2011)
Cédric Killian, Camel Tanougast, M. Monteiro, Camille Diou, Abbas Dandache, S. Jovanovic
Behavioral modeling and C-VHDL co-simulation of Network on Chip on FPGA for Education. ReCoSoC (2010)
Mohsin Amin, Camille Diou, Fabrice Monteiro, Abbas Ramazani, Abbas Dandache
A Self-Checking HW Journal for a Fault Tolerant Processor Architecture. ReCoSoC (2010)
Mohsin Amin, Fabrice Monteiro, Camille Diou, Abbas Ramazani, Abbas Dandache
A HW/SW mixed mechanism to improve the dependability of a stack processor. ICECS (2009)
Abbas Ramazani, Mohsin Amin, Fabrice Monteiro, Camille Diou, Abbas Dandache
A fault tolerant journalized stack processor architecture. IOLTS (2009)
Mehdi Jallouli, Camille Diou, Fabrice Monteiro
Stack processor architecture and development methods suitable for dependable applications. ReCoSoC (2007)
Mazen Youssef, Fabrice Monteiro, Abbas Dandache, Camille Diou
A cost-effective parallel architecture for the CodeRAKE receiver. ICECS (2007)
Mazen Youssef, Camille Diou, Fabrice Monteiro, Abbas Dandache
CodeRAKE: a new small-area scalable architecture for the multi-user/multi-code RAKE receiver. ICECS (2006)
Abbas Ramazani, Fabrice Monteiro, Camille Diou, Abbas Dandache
A multiprocessor architecture for fast packet processing. ICECS (2005)
Gilles Sassatelli, Lionel Torres, Pascal Benoit, Thierry Gil, Camille Diou, Gaston Cambon, Jérôme Galy
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications. DATE (2002)
Camille Diou, Lionel Torres, Michel Robert
An embedded core for the 2D wavelet transform. ETFA (2) (2001)
Gilles Sassatelli, Lionel Torres, Jérôme Galy, Gaston Cambon, Camille Diou
The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems. FPL (2001)
Camille Diou, Lionel Torres, Michel Robert
A Wavelet Core for Video Processing. ICIP (2000)
Camille Diou, Lionel Torres, Michel Robert
Implementation of a Wavelet Transform Architecture for Image Processing. VLSI (1999)