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Behavioral modeling and C-VHDL co-simulation of Network on Chip on FPGA for Education.
Cédric Killian
Camel Tanougast
M. Monteiro
Camille Diou
Abbas Dandache
S. Jovanovic
Published in:
ReCoSoC (2010)
Keyphrases
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network on chip
hardware implementation
network simulator
hardware design
field programmable gate array
signal processing
fpga implementation
high speed
packet switched
routing algorithm
multistage
image processing
low cost
peer to peer
simulation model
embedded systems