Bjørnar Hernes

Publication Activity (10 Years)

Years Active: 2001-2013
Publications (10 Years): 0

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Publications

Rune Kaald, Bjørnar Hernes, Christian Holdo, Frode Telstø, Ivar Løkken
A 500 MS/s 76dB SNDR continuous time delta sigma modulator with 10MHz signal bandwidth in 0.18μm CMOS. CICC (2013)
Terje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor
A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18µm Digital CMOS CoRR (2007)
Bjørnar Hernes, Johnny Bjørnsen, Terje N. Andersen, Anders Vinje, Havard Korsvoll, Frode Telstø, Atle Briskemyr, Christian Holdo, Øystein Moldsvor
A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13μm CMOS. ISSCC (2007)
Ivar Løkken, Anders Vinje, Trond Sæther, Bjørnar Hernes
Quantizer Nonoverload Criteria in Sigma-Delta Modulators. IEEE Trans. Circuits Syst. II Express Briefs (12) (2006)
Terje Nortvedt Andersen, Bjørnar Hernes, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Øystein Moldsvor
A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS. IEEE J. Solid State Circuits 40 (7) (2005)
Bjørnar Hernes, Willy M. C. Sansen
Distortion in single-, two- and three-stage amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2005)
Terje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor
A 97mW 110MS/s 12b pipeline ADC implemented in 0.18μm digital CMOS. ESSCIRC (2004)
Terje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor
A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOS. DATE (2004)
Thomas E. Bonnerud, Bjørnar Hernes, Trond Ytterdal
A mixed-signal, functional level simulation framework based on SystemC for system-on-a-chip applications. CICC (2001)
Bjørnar Hernes, Øystein Moldsvor, Trond Sæther
A -80 dB HD3 opamp in 3.3 V CMOS technology using tail current compensation. ISCAS (1) (2001)