A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS.
Terje Nortvedt AndersenBjørnar HernesAtle BriskemyrFrode TelstøJohnny BjørnsenThomas E. BonnerudØystein MoldsvorPublished in: IEEE J. Solid State Circuits (2005)
Keyphrases
- cost efficient
- analog to digital converter
- high speed
- low power
- mixed signal
- image sensor
- vlsi circuits
- spl times
- single chip
- cmos image sensor
- cmos technology
- power consumption
- governmental organizations
- shift register
- low cost
- high speed networks
- frame rate
- delay insensitive
- wide dynamic range
- multi channel
- pipeline architecture