Bernard Lepley

Publication Activity (10 Years)

Years Active: 1998-2004
Publications (10 Years): 0

Publications

Amine M'sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley
Designing a High Speed Decoder for Cyclic Codes. IOLTS (2004)
Amine M'sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley
Design of a high speed parallel encoder for convolutional codes. Microelectron. J. 35 (2) (2004)
Abbas Ramazani, Fabrice Monteiro, Abbas Dandache, Bernard Lepley
A methodology to design a multimedia processor core. ICECS (2003)
Amine M'sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley
A High Speed Encoder for Recursive Systematic Convolutive Codes. IOLTW (2002)
Fabrice Monteiro, Abbas Dandache, Bernard Lepley
Fast Configurable Polynomial Division for Error Control Coding Applications. IOLTW (2001)
Fabrice Monteiro, Abbas Dandache, Amine M'sir, Bernard Lepley
A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division. ICECS (2001)
T. Vallino, Abbas Dandache, J. P. Delahaye, Fabrice Monteiro, Bernard Lepley
A Stamping Technique to Increase the Error Correction Capacity of the (127, k, d) RS Code. IOLTW (2000)
Abbas Dandache, Fabrice Monteiro, Bernard Lepley
Design of a selective digital filter for a DAVIC compliant modem. ICECS (2000)
J.-Ph. Lambert, Abbas Dandache, Fabrice Monteiro, Bernard Lepley
Design of radiofrequency stages for a high rate digital modem. ICECS (1998)
S. Philip, Fabrice Monteiro, Abbas Dandache, Bernard Lepley
A high-speed parallel DSP architecture dedicated to digital modem applications. ICECS (1998)