A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division.
Fabrice MonteiroAbbas DandacheAmine M'sirBernard LepleyPublished in: ICECS (2001)
Keyphrases
- pipelined architecture
- hardware implementation
- field programmable gate array
- fpga implementation
- hardware architecture
- fpga technology
- dedicated hardware
- efficient implementation
- fpga device
- software implementation
- image processing algorithms
- high speed
- real time
- xilinx virtex
- signal processing
- hardware design
- neural network
- hardware software co design
- real time image processing
- parallel architecture
- low cost
- learning algorithm
- data sets