B. P. Harish

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 7

Top Topics

Max Flow Min Cut

Spatially Aware

Top Venues

Int. J. Circuit Theory Appl.

Publications

H. T. Manohara, B. P. Harish
A Novel Feasibility Test for Energy Minimization of Real-Time Mixed Task Sets for DVS-Enabled Uniprocessor System. J. Circuits Syst. Comput. 31 (3) (2022)
Harsha M. V., B. P. Harish
Artificial Neural Network Model for Design Optimization of 2-stage Op-amp. VDAT (2020)
Anala M. Reddy, B. P. Harish
Process-induced variability modeling of subthreshold leakage power considering device stacking. Int. J. Circuit Theory Appl. 48 (5) (2020)
Anala M., B. P. Harish
Process Variation-Aware Analytical Modeling of Subthreshold Leakage Power. PATMOS (2019)
H. T. Manohara, B. P. Harish
Dynamic Supply Voltage Level Generation for Minimum Energy Real Time Tasks using Geometric Programming. SoCC (2019)
Harsha M. V., B. P. Harish
An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-Stage Op-Amp Design Automation. ISVLSI (2018)
Anala M., B. P. Harish
Analytical Modeling of Process Variability in Subthreshold Regime for Ultra Low Power Applications. APCCAS (2018)
B. P. Harish, Navakanta Bhat, Mahesh B. Patil
Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits. ISCAS (2009)
B. P. Harish, Navakanta Bhat, Mahesh B. Patil
Hybrid-CV Modeling for Estimating the Variability in Dynamic Power. J. Low Power Electron. 4 (3) (2008)
B. P. Harish, Navakanta Bhat, Mahesh B. Patil
Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs. ICCTA (2007)
B. P. Harish, Navakanta Bhat, Mahesh B. Patil
On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (3) (2007)