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Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs.
B. P. Harish
Navakanta Bhat
Mahesh B. Patil
Published in:
ICCTA (2007)
Keyphrases
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nm technology
power consumption
power dissipation
cmos technology
low power
clock gating
real time
computer vision
high speed
power reduction
chip design