Avaneendra Gupta

Publication Activity (10 Years)

Years Active: 1996-2000
Publications (10 Years): 0

Publications

Avaneendra Gupta, John P. Hayes
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells. ACM Trans. Design Autom. Electr. Syst. 5 (3) (2000)
Avaneendra Gupta, John P. Hayes
Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. VLSI Design (1999)
Avaneendra Gupta, John P. Hayes
Optimal 2-D cell layout with integrated transistor folding. ICCAD (1998)
Avaneendra Gupta, John P. Hayes
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. VLSI Design (1997)
Avaneendra Gupta, John P. Hayes
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. DAC (1997)
Avaneendra Gupta, John P. Hayes
Width minimization of two-dimensional CMOS cells using integer programming. ICCAD (1996)
Avaneendra Gupta, Siang-Chun The, John P. Hayes
XPRESS: A Cell Layout Generator with Integrated Transistor Folding. ED&TC (1996)