Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells.

Avaneendra Gupta John P. Hayes

Published in: VLSI Design (1999)

Keyphrases

three dimensional
hierarchically organized
low cost
high speed
hierarchical structure
power consumption
hierarchical clustering
vlsi circuits
circuit design
global optimum
inter cell
analog vlsi
program synthesis
image sensor
hierarchical model
texture synthesis
low power
coarse to fine