CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells.

Avaneendra Gupta John P. Hayes

Published in: DAC (1997)

Keyphrases

three dimensional
inter cell
power consumption
video clips
low cost
high speed
multi dimensional
neural network
low power
circuit design
low voltage
delay insensitive
vlsi circuits
feature vectors
power supply
pseudorandom
layout design
random access memory
data sets