Antonis Tsigkanos

Publication Activity (10 Years)

Years Active: 2015-2022
Publications (10 Years): 8

Top Topics

Data Processing

Entropy Constrained

Fpga Technology

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Antonis M. Paschalis, Panagiotis Chatziantoniou, Dimitris Theodoropoulos, Antonis Tsigkanos, Nektarios Kranitis
High-Performance Hardware Accelerators for Next Generation On-Board Data Processing. VLSI-SoC (2022)
Panagiotis Chatziantoniou, Antonis Tsigkanos, Dimitris Theodoropoulos, Nektarios Kranitis, Antonis M. Paschalis
An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology. IEEE Trans. Aerosp. Electron. Syst. 58 (6) (2022)
Panagiotis Chatziantoniou, Antonis Tsigkanos, Dimitris Theodoropoulos, Nektarios Kranitis, Antonis M. Paschalis
An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology. CoRR (2022)
Antonis Tsigkanos, Nektarios Kranitis, George Theodorou, Antonis M. Paschalis
A 3.3 Gbps CCSDS 123.0-B-1 Multispectral & Hyperspectral Image Compression Hardware Accelerator on a Space-Grade SRAM FPGA. IEEE Trans. Emerg. Top. Comput. 9 (1) (2021)
Antonis Tsigkanos, Nektarios Kranitis, Dimitris Theodoropoulos, Antonis M. Paschalis
High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1. IEEE Trans. Very Large Scale Integr. Syst. 28 (11) (2020)
Dimitris Theodoropoulos, Nektarios Kranitis, Antonis Tsigkanos, Antonis M. Paschalis
Efficient Architectures for Multigigabit CCSDS LDPC Encoders. IEEE Trans. Very Large Scale Integr. Syst. 28 (5) (2020)
Dimitris Theodoropoulos, Nektarios Kranitis, Antonis Tsigkanos, Antonis M. Paschalis
Efficient LDPC Encoder Designs for Magnetic Recording Media. DFT (2020)
Ioannis Tsounis, Antonis Tsigkanos, Vasileios Vlagkoulis, Mihalis Psarakis, Nektarios Kranitis, Antonis M. Paschalis
Analyzing the Resilience to SEUs of an Image Data Compression Core in a COTS SRAM FPGA. AHS (2019)
Nektarios Kranitis, Antonis Tsigkanos, George Theodorou, Ioannis Sideris, Antonis M. Paschalis
A single chip dependable and adaptable payload Data Processing Unit. IOLTS (2015)