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Analyzing the Resilience to SEUs of an Image Data Compression Core in a COTS SRAM FPGA.
Ioannis Tsounis
Antonis Tsigkanos
Vasileios Vlagkoulis
Mihalis Psarakis
Nektarios Kranitis
Antonis M. Paschalis
Published in:
AHS (2019)
Keyphrases
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image data compression
image compression
block coding
power consumption
power reduction
high speed
hardware implementation
signal processing
data transmission
field programmable gate array
image processing
low power
subband
image coding
data acquisition
fault tolerance
high quality