Andreas Dandalis

Publication Activity (10 Years)

Years Active: 1997-2005
Publications (10 Years): 0

Publications

Andreas Dandalis, Viktor K. Prasanna
Configuration compression for FPGA-based embedded systems. IEEE Trans. Very Large Scale Integr. Syst. 13 (12) (2005)
Andreas Dandalis, Viktor K. Prasanna
An adaptive cryptographic engine for internet protocol security architectures. ACM Trans. Design Autom. Electr. Syst. 9 (3) (2004)
Andreas Dandalis, Viktor K. Prasanna
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers. ACM Trans. Design Autom. Electr. Syst. 7 (4) (2002)
Andreas Dandalis, Viktor K. Prasanna
Configuration compression for FPGA-based embedded systems. FPGA (2001)
Andreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam
Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. FPL (2001)
Mark Redekopp, Andreas Dandalis
A Parallel Pipelined SAT Solver for FPGAs. FPL (2000)
Andreas Dandalis, Viktor K. Prasanna, José D. P. Rolim
An Adaptive Cryptographic Engine for IPSec Architectures. FCCM (2000)
Andreas Dandalis, Viktor K. Prasanna, José D. P. Rolim
A Comparative Study of Performance of AES Final Candidates Using FPGAs. CHES (2000)
Sameer Wadhwa, Andreas Dandalis
Efficient Self-Reconfigurable Implementations Using On-chip Memory. FPL (2000)
Andreas Dandalis, Alessandro Mei, Viktor K. Prasanna
Domain Specific Mapping for Solving Graph Problems on Reconfigurable Devices. IPPS/SPDP Workshops (1999)
Andreas Dandalis, Viktor K. Prasanna
Mapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures. FCCM (1998)
Andreas Dandalis, Viktor K. Prasanna
Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures. FPL (1998)
Andreas Dandalis, Viktor K. Prasanna
Fast parallel implementation of DFT using configurable devices. FPL (1997)