Amila Edirisuriya

Publication Activity (10 Years)

Years Active: 2012-2017
Publications (10 Years): 3

Top Topics

Karhunen Loeve Transform

Hardware Architecture

Image Compression

Exact Computation

Top Venues

IEEE Trans. Circuits Syst. Video Technol.

IEEE Trans. Circuits Syst. I Regul. Pap.

J. Electr. Comput. Eng.

Publications

Renato J. Cintra, Fábio M. Bayer, Arjuna Madanayake, Uma Sadhvi Potluri, Amila Edirisuriya
Fast Algorithms and Architectures for 8-Point DST-II/DST-VII Approximations. J. Circuits Syst. Comput. 26 (3) (2017)
Amila Edirisuriya, Arjuna Madanayake, Renato J. Cintra, Vassil S. Dimitrov
A Single-Channel Architecture for Algebraic Integer Based 8×8 2-D DCT Computation. CoRR (2017)
Fábio M. Bayer, Renato J. Cintra, Amila Edirisuriya, Arjuna Madanayake
A Digital Hardware Fast Algorithm and FPGA-based Prototype for a Novel 16-point Approximate DCT for Image Compression Applications. CoRR (2017)
Uma Sadhvi Potluri, Arjuna Madanayake, Renato J. Cintra, Fábio M. Bayer, Sunera Kulasekera, Amila Edirisuriya
Improved 8-point Approximate DCT for Image and Video Compression Requiring Only 14 Additions. CoRR (2015)
Arjuna Madanayake, Renato J. Cintra, Denis Onen, Vassil S. Dimitrov, Nilanka T. Rajapaksha, Leonard T. Bruton, Amila Edirisuriya
A Row-parallel 8×8 2-D DCT Architecture Using Algebraic Integer Based Exact Computation. CoRR (2015)
Uma Sadhvi Potluri, Arjuna Madanayake, Renato J. Cintra, Fábio M. Bayer, Sunera Kulasekera, Amila Edirisuriya
Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2014)
Amila Edirisuriya, Arjuna Madanayake, Renato J. Cintra, Vassil S. Dimitrov, Nilanka T. Rajapaksha
A Single-Channel Architecture for Algebraic Integer-Based 8 × 8 2-D DCT Computation. IEEE Trans. Circuits Syst. Video Technol. 23 (12) (2013)
Nilanka T. Rajapaksha, Amila Edirisuriya, Arjuna Madanayake, Renato J. Cintra, Denis Onen, Ihab Amer, Vassil S. Dimitrov
Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA. J. Electr. Comput. Eng. 2013 (2013)
Arjuna Madanayake, Renato J. Cintra, Denis Onen, Vassil S. Dimitrov, Nilanka T. Rajapaksha, Leonard T. Bruton, Amila Edirisuriya
A Row-Parallel 8 × 8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation. IEEE Trans. Circuits Syst. Video Technol. 22 (6) (2012)