Nilanka T. Rajapaksha

Publication Activity (10 Years)

Years Active: 2011-2017
Publications (10 Years): 3

Top Topics

Signal Processing

Exact Computation

Pipelined Architecture

Cosine Transform

Top Venues

IEEE Trans. Circuits Syst. Video Technol.

Multidimens. Syst. Signal Process.

IEEE Trans. Computers

Publications

Sewwandi Wijayaratna, Nilanka T. Rajapaksha, Arjuna Madanayake, Len T. Bruton
Fast FPGA-architecture for fan/beam-steering in wave-digital RF aperture arrays. Multidimens. Syst. Signal Process. 28 (2) (2017)
Nilanka T. Rajapaksha, Arjuna Madanayake, Renato J. Cintra, Jithra Adikari, Vassil S. Dimitrov
VLSI Computational Architectures for the Arithmetic Cosine Transform. CoRR (2017)
Diego F. G. Coelho, Renato J. Cintra, Nilanka T. Rajapaksha, Gihan J. Mendis, Arjuna Madanayake, Vassil S. Dimitrov
DFT Computation Using Gauss-Eisenstein Basis: FFT Algorithms and VLSI Architectures. IEEE Trans. Computers 66 (8) (2017)
Nilanka T. Rajapaksha, Arjuna Madanayake, Renato J. Cintra, Jithra Adikari, Vassil S. Dimitrov
VLSI Computational Architectures for the Arithmetic Cosine Transform. IEEE Trans. Computers 64 (9) (2015)
Arjuna Madanayake, Renato J. Cintra, Denis Onen, Vassil S. Dimitrov, Nilanka T. Rajapaksha, Leonard T. Bruton, Amila Edirisuriya
A Row-parallel 8×8 2-D DCT Architecture Using Algebraic Integer Based Exact Computation. CoRR (2015)
Nilanka T. Rajapaksha, Arjuna Madanayake, Leonard T. Bruton
Systolic array architecture for steerable multibeam VHF wave-digital RF apertures. IEEE Trans. Aerosp. Electron. Syst. 51 (1) (2015)
Nilanka T. Rajapaksha, Arjuna Madanayake, Leonard T. Bruton
2D space-time wave-digital multi-fan filter banks for signals consisting of multiple plane waves. Multidimens. Syst. Signal Process. 25 (1) (2014)
Amila Edirisuriya, Arjuna Madanayake, Renato J. Cintra, Vassil S. Dimitrov, Nilanka T. Rajapaksha
A Single-Channel Architecture for Algebraic Integer-Based 8 × 8 2-D DCT Computation. IEEE Trans. Circuits Syst. Video Technol. 23 (12) (2013)
Nilanka T. Rajapaksha, Amila Edirisuriya, Arjuna Madanayake, Renato J. Cintra, Denis Onen, Ihab Amer, Vassil S. Dimitrov
Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA. J. Electr. Comput. Eng. 2013 (2013)
Arjuna Madanayake, Renato J. Cintra, Denis Onen, Vassil S. Dimitrov, Nilanka T. Rajapaksha, Leonard T. Bruton, Amila Edirisuriya
A Row-Parallel 8 × 8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation. IEEE Trans. Circuits Syst. Video Technol. 22 (6) (2012)
Nilanka T. Rajapaksha, Arjuna Madanayake
Asynchronous-QDI 2D IIR digital filter circuits. ISCAS (2011)