Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA.
Nilanka T. RajapakshaAmila EdirisuriyaArjuna MadanayakeRenato J. CintraDenis OnenIhab AmerVassil S. DimitrovPublished in: J. Electr. Comput. Eng. (2013)
Keyphrases
- video compression
- hardware implementation
- high speed
- real time image processing
- discrete cosine transform
- field programmable gate array
- delay insensitive
- signal processing
- dedicated hardware
- hardware architecture
- low power consumption
- asynchronous communication
- asynchronous circuits
- hardware design
- digital signal
- video data
- algebraic geometry
- higher order
- systolic array
- pipelined architecture
- mathematical theory
- state machines
- high definition
- multimedia
- data acquisition
- image compression
- motion estimation
- optimal solution