Login / Signup
Performance evaluation of the low-voltage CML D-latch topology.
Massimo Alioto
Rosario Mita
Gaetano Palumbo
Published in:
Integr. (2003)
Keyphrases
</>
low voltage
power consumption
power management
power line
design considerations
cmos technology
low power
high density
image processing
data center
parallel processing
energy saving