A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system.
Yen-Liang ChenTing-Jyun JhengCheng-Zhou ZhanAn-Yeu WuPublished in: ESSCIRC (2010)
Keyphrases
- low cost
- singular value decomposition
- power consumption
- floating point arithmetic
- power reduction
- clock frequency
- floating point
- analog vlsi
- rms error
- high speed
- wireless lan
- reconfigurable hardware
- hardware implementation
- functional units
- least squares
- power dissipation
- general purpose
- low power
- power supply
- single chip
- programmable logic
- systolic array
- hardware and software
- reconfigurable architecture
- high density
- computer society
- field programmable gate array
- average error
- root mean square
- dimensionality reduction
- hd video
- localization error
- intelligent agent technology
- real time
- embedded systems
- power plant
- singular values
- evolvable hardware
- vlsi implementation
- instruction set
- cmos technology
- fine grain
- physical design
- circuit design