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Enhancing delay fault coverage through low-power segmented scan.
Zhuo Zhang
Sudhakar M. Reddy
Irith Pomeranz
Janusz Rajski
Bashir M. Al-Hashimi
Published in:
IET Comput. Digit. Tech. (2007)
Keyphrases
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low power
power dissipation
power consumption
high speed
low cost
single chip
high power
digital signal processing
wireless transmission
low power consumption
logic circuits
vlsi architecture
vlsi circuits
gate array
message passing
mixed signal