Physical verification flow for hierarchical analog ic design constraints.
Volker Meyer zu BextenMarkus TristlGöran JerkeHartmut MarquardtDina MedhatPublished in: ASP-DAC (2015)
Keyphrases
- real world
- circuit design
- engineering design
- design methodology
- signal processing
- physical constraints
- design principles
- functional verification
- database
- digital computer
- flow patterns
- formal methods
- design decisions
- constrained optimization
- geometric constraints
- hierarchical clustering
- computer aided
- knowledge based systems
- user interface