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A 64-MHz clock-rate ΣΔ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency.
Sandeep K. Gupta
Victor Fong
Published in:
IEEE J. Solid State Circuits (2002)
Keyphrases
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high speed
noise ratio
high frequency
low frequency
clock frequency
duty cycle
database
power consumption
fpga device
non stationary
image processing
signal to noise ratio
frequency spectrum