A sub-0.75°RMS-phase-error differentially-tuned fractional-N synthesizer with on-chip LDO regulator and analog-enhanced AFC technique.
Lei LuLingbu MengLiang ZouHao MinZhangwen TangPublished in: CICC (2009)
Keyphrases
- analog vlsi
- root mean square
- circuit design
- mixed signal
- high speed
- error rate
- steady state
- cmos image sensor
- low cost
- error bounds
- high density
- closed loop
- multi channel
- rms error
- focal plane
- image sensor
- training phase
- frequency modulation
- multiscale
- real time
- ibm power processor
- vlsi architecture
- learning phase
- error analysis
- dynamical systems
- neural network