A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation.

Rami A. Abdallah Naresh R. Shanbhag

Published in: CICC (2012)

Keyphrases

error compensation
cmos technology
nm technology
low power
parallel processing
high speed
metal oxide semiconductor
single chip
power consumption
low voltage
leakage current
low cost
random access memory
integrated circuit
silicon on insulator
image sensor
digital signal processing
design considerations
heart rate