A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access.
Keiichi KushidaOsamu HirabayashiFumihiko TachibanaHiroyuki HaraAtsushi KawasumiAzuma SuzukiYasuhisa TakeyamaYuki FujimuraYusuke NikiMiyako ShizunoShinichi SasakiTomoaki YabePublished in: A-SSCC (2011)