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A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement.
Jixuan Li
Jiabao Chen
Ka-Fai Un
Wei-Han Yu
Pui-In Mak
Rui Paulo Martins
Published in:
A-SSCC (2021)
Keyphrases
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signal processing
field programmable gate array
multi layer
image processing
digital signal processing
multiscale
computational complexity
wireless sensor networks
general purpose
low cost
hardware implementation
high efficiency
application specific