A new RISC processor architecture for MPEG-2 decoding.
Kunihiro YamadaMasanori KojimaToru ShimizuFumiaki SatoTadanori MizunoPublished in: IEEE Trans. Consumer Electron. (2002)
Keyphrases
- instruction set
- video decoder
- computation intensive
- low power consumption
- hardware architecture
- floating point
- application specific
- computer architecture
- level parallelism
- parallel architecture
- multi processor
- single chip
- high speed
- low cost
- memory subsystem
- hardware implementation
- video sequences
- industry standard
- parallel processing
- error detection
- memory access
- real time
- video objects
- computational complexity
- multimedia