A hardware Memetic accelerator for VLSI circuit partitioning.
Stephen CoeShawki AreibiMedhat MoussaPublished in: Comput. Electr. Eng. (2007)
Keyphrases
- chip design
- circuit design
- gate array
- high speed
- vlsi implementation
- vlsi circuits
- field programmable gate array
- digital circuits
- single chip
- vlsi architecture
- hardware and software
- low power
- evolvable hardware
- hardware description language
- hardware implementation
- signal processing
- low cost
- power dissipation
- differential evolution
- physical design
- image processing algorithms
- memetic algorithm
- parallel implementation
- real time
- hardware software co design
- computing systems
- computer systems
- image processing
- programmable logic
- neural network
- vlsi design
- particle swarm optimizer
- design methodology
- logic circuits
- computing platform
- computing power