An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface.
Young-Sik KimSeon-Kyoo LeeSeung-Jun BaeYoung-Soo SohnJung-Bae LeeJoo-Sun ChoiHong-June ParkJae-Yoon SimPublished in: ISSCC (2012)
Keyphrases
- high speed
- low power
- cmos technology
- gigabit ethernet
- low voltage
- data acquisition
- ultra low power
- frame rate
- user interface
- dynamic random access memory
- parallel implementation
- parallel processing
- high density
- focal plane
- parallel computing
- single chip
- high speed networks
- user friendly
- real time
- shared memory
- computer architecture
- main memory
- data skew
- power consumption