A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design.
I-Chyn WeyYu-Sheng YangBing-Chen WuChien-Chang PengPublished in: Microelectron. J. (2014)
Keyphrases
- low power
- circuit design
- power consumption
- low cost
- high speed
- power dissipation
- digital signal processing
- high power
- single chip
- power reduction
- wireless transmission
- vlsi circuits
- vlsi architecture
- digital circuits
- cmos technology
- low power consumption
- real time
- mixed signal
- ultra low power
- gate array
- delay insensitive
- design automation
- power saving
- low complexity