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On the in-field functional testing of decode units in pipelined RISC processors.

Paolo BernardiRiccardo CantoroLyl M. Ciganda BrascaErnesto SánchezMatteo Sonza ReordaSergio de LucaRenato MeregalliAlessandro Sansonetti
Published in: DFT (2014)
Keyphrases
  • instruction set
  • processing units
  • parallel algorithm
  • parallel processing
  • test data
  • high performance computing
  • multiprocessor systems
  • instruction set architecture