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A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.
Kazutoshi Kobayashi
Manabu Kotani
Kazuya Katsuki
Y. Takatsukasa
K. Ogata
Yuuri Sugihara
Hidetoshi Onodera
Published in:
FPL (2006)
Keyphrases
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high speed
low cost
real time
image enhancement
computer vision
image processing
mobile devices
processing speed
reconfigurable hardware
reconfigurable architecture
general purpose
image quality
electron microscopy
floating gate