Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS.
Taehui NaByungkyu SongSara ChoiJung Pill KimSeung-Hyuk KangSeong-Ook JungPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2019)
Keyphrases
- nm technology
- analog to digital converter
- random access memory
- power consumption
- design considerations
- cmos technology
- embedded dram
- image sensor
- low power
- real time
- management system
- processor core
- bloom filter
- low cost
- power dissipation
- low voltage
- high speed
- memory management
- virtual memory
- protection scheme
- dynamic range
- line segments