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Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands.
Darjn Esposito
Davide De Caro
Antonio Giuseppe Maria Strollo
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2016)
Keyphrases
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bit parallel
pattern matching
parallel processing
data structure
low latency
shared memory
information systems
response time
regular expressions
parallel implementation
massively parallel
parallel execution
load balance
neural network
genetic algorithm
parallel computation