Login / Signup
High Performance Circuit Techniques for Nueral Front-End Design in 65nm CMOS.
Rajasekhar Nagulapalli
Khaled Hayatleh
Steve Barker
Saddam Zourob
Nabil Yassine
B. Naresh Kumar Reddy
Published in:
ICCCNT (2018)
Keyphrases
</>
circuit design
cmos technology
nm technology
high speed
low power
chip design
engineering design
neural network
building blocks
case study
hardware and software
design process
digital circuits
power dissipation
power consumption
logic circuits
logic synthesis
low cost