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Nabil Yassine
ORCID
Publication Activity (10 Years)
Years Active: 2018-2022
Publications (10 Years): 9
Top Topics
Cmos Technology
Topic Drift
Low Cost
Spl Times
Top Venues
J. Circuits Syst. Comput.
ICCCNT
ISCAS
VDAT
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Publications
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Rajasekhar Nagulapalli
,
Khaled Hayatleh
,
Nabil Yassine
,
S. Barker
C Temperature coefficient in 28nm CMOS.
ISCAS
(2022)
Rajasekhar Nagulapalli
,
Khaled Hayatleh
,
Steve Barker
,
Amr A. Tammam
,
F. John Lidgey
,
Nabil Yassine
A High-Sensitivity and Low-Power Circuit for the Measurement of Abnormal Blood Cell Levels.
J. Circuits Syst. Comput.
29 (4) (2020)
Rajasekhar Nagulapalli
,
Khaled Hayatleh
,
Steve Barker
,
Amr A. Tammam
,
Nabil Yassine
,
Bilal Yassine
,
Mohamed Ben-Esmael
A Low Noise Amplifier Suitable for Biomedical Recording Analog Front-End in 65nm CMOS Technology.
J. Circuits Syst. Comput.
28 (8) (2019)
Rajasekhar Nagulapalli
,
Khaled Hayatleh
,
Steve Barker
,
Bilal Yassine
,
Saddam Zourob
,
Sumathi Raparthy
,
Nabil Yassine
A Start-up Assisted Fully Differential Folded Cascode Opamp.
J. Circuits Syst. Comput.
28 (10) (2019)
Khaled Hayatleh
,
Saddam Zourob
,
Rajasekhar Nagulapalli
,
Steve Barker
,
Nabil Yassine
,
Pantelis Georgiou
,
F. J. Lidgey
A High-Performance Skin Impedance Measurement Circuit for Biomedical Applications.
J. Circuits Syst. Comput.
28 (7) (2019)
Rajasekhar Nagulapalli
,
Khaled Hayatleh
,
Steve Barker
,
Saddam Zourob
,
Nabil Yassine
,
B. Naresh Kumar Reddy
A Technique to Reduce the Capacitor Size in Two Stage Miller Compensated Opamp.
ICCCNT
(2018)
Rajasekhar Nagulapalli
,
Khaled Hayatleh
,
Steve Barker
,
Sumathi Raparthy
,
Nabil Yassine
,
John Lidgey
A 0.6 V MOS-Only Voltage Reference for Biomedical Applications with 40 ppm/∘C Temperature Drift.
J. Circuits Syst. Comput.
27 (8) (2018)
Rajasekhar Nagulapalli
,
Khaled Hayatleh
,
Steve Barker
,
Saddam Zourob
,
Nabil Yassine
,
B. Naresh Kumar Reddy
A 31 ppm/° C Pure CMOS Bandgap Reference by Exploiting Beta-Multiplier.
VDAT
(2018)
Rajasekhar Nagulapalli
,
Khaled Hayatleh
,
Steve Barker
,
Saddam Zourob
,
Nabil Yassine
,
B. Naresh Kumar Reddy
High Performance Circuit Techniques for Nueral Front-End Design in 65nm CMOS.
ICCCNT
(2018)