Using on-chip test pattern compression for full scan SoC designs.
Helmut LangJens PfeifferJeff MaguirePublished in: ITC (2000)
Keyphrases
- application specific integrated circuits
- test data
- high speed
- data compression
- compression ratio
- low power
- associative memory
- pattern matching
- test cases
- image compression
- low cost
- compression algorithm
- real time
- hardware and software
- compression rate
- physical design
- hardware software co design
- nm technology
- image processing